1. Universidad Antonio Nariño
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dc.contributor.advisorDuarte Gonzáles, Mario Enrrique-
dc.creatorGalindo Rodríguez, María José-
dc.date.accessioned2021-03-02T14:20:56Z-
dc.date.available2021-03-02T14:20:56Z-
dc.date.created2020-07-21-
dc.identifier.urihttp://repositorio.uan.edu.co/handle/123456789/2213-
dc.description.abstractAlgebra of multiple logical values emerged as a solution to the problems present in binary circuits (2 logical levels): misuse of area and power in digital integrated circuits. Among the possible alternatives, several proposals for quaternary algebras (4 logical levels) have been presented, together with their corresponding logical operators (gates); which have been designed and implemented in both current and voltage modes, using CMOS technology. The best configuration for logic gates is in voltage mode because there is less power dissipation, as reported in the literature. In this work, a design was proposed for the circuits of the quaternary gates implementing CMOS technology in voltage mode with a smaller required area than the gates reported in recent works, the correct operation of the circuits was verified using the CADENCE Virtuoso program, as well as, the electrical characteristics: slew rate and power, by means of simulation. Finally, to evaluate the correct operation of the circuits, a quaternary demultiplexer was designed, built and simulated with the same tool.es_ES
dc.description.sponsorshipOtroes_ES
dc.description.tableofcontentsEl álgebra de múltiples valores lógicos surgió como una solución a los problemas presentes en los circuitos binarios (2 niveles lógicos): mal uso de área y potencia en circuitos integrados digitales. Entre las posibles alternativas se han presentado varias propuestas de álgebras cuaternarias (4 niveles lógicos), junto con sus correspondientes operadores (compuertas) lógicos; los cuales han sido diseñadas e implementadas tanto en modo corriente como en modo voltaje, utilizando tecnología CMOS. La mejor configuración para la compuertas lógicas es en modo voltaje debido que hay una menor disipación de potencia, tal como se ha reportado en la literatura. En este trabajo, se propuso un diseño para los circuitos de las compuertas cuaternarias implementando tecnología CMOS en modo voltaje con área requerida menor que las compuertas reportadas en trabajos recientes, se verificó el correcto funcionamiento de los circuito utilizando el programa CADENCE Virtuoso, así como, las características eléctricas: slew rate y potencia, por medio de simulación. Por último, para evaluar el funcionamiento correcto de los circuitos se diseñó, construyó y simuló con la misma herramienta un demultiplexor cuaternario.es_ES
dc.language.isospaes_ES
dc.publisherUniversidad Antonio Nariñoes_ES
dc.rightsAtribución-NoComercial-SinDerivadas 3.0 Estados Unidos de América*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/us/*
dc.sourceinstname:Universidad Antonio Nariñoes_ES
dc.sourcereponame:Repositorio Institucional UANes_ES
dc.sourceinstname:Universidad Antonio Nariñoes_ES
dc.sourcereponame:Repositorio Institucional UANes_ES
dc.subjectAlgebra de multiples valores lógicos.es_ES
dc.titleDiseño de compuertas lógicas cuaternarias CMOS en modo voltajees_ES
dc.publisher.programIngeniería Electrónicaes_ES
dc.rights.accesRightsopenAccesses_ES
dc.subject.keywordAlgebra of multiple logical values.es_ES
dc.type.spaTrabajo de grado (Pregrado y/o Especialización)es_ES
dc.type.hasVersioninfo:eu-repo/semantics/acceptedVersiones_ES
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dc.description.degreenameIngeniero(a) Electrónico(a)es_ES
dc.description.degreelevelPregradoes_ES
dc.publisher.facultyFacultad de Ingeniería Mecánica, Electrónica y Biomédicaes_ES
dc.description.funderCosto total del proyecto $3’503.182. Financiación propia $1’635.000. Financiación UAN $980.000es_ES
dc.description.notesPresenciales_ES
dc.publisher.campusBogotá - Sur-
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