Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje

Abstract

Algebra of multiple logical values emerged as a solution to the problems present in binary circuits (2 logical levels): misuse of area and power in digital integrated circuits. Among the possible alternatives, several proposals for quaternary algebras (4 logical levels) have been presented, together with their corresponding logical operators (gates); which have been designed and implemented in both current and voltage modes, using CMOS technology. The best configuration for logic gates is in voltage mode because there is less power dissipation, as reported in the literature. In this work, a design was proposed for the circuits of the quaternary gates implementing CMOS technology in voltage mode with a smaller required area than the gates reported in recent works, the correct operation of the circuits was verified using the CADENCE Virtuoso program, as well as, the electrical characteristics: slew rate and power, by means of simulation. Finally, to evaluate the correct operation of the circuits, a quaternary demultiplexer was designed, built and simulated with the same tool.